The semiconductor device industry has a market driven need to reduce the size of devices such as transistors. Smaller transistors result in improved operational speed and clock rate, and reduced power requirements in both the standby and operational modes. To reduce transistor size, the thickness of the silicon dioxide (SiO2) gate dielectric is reduced in proportion to the shrinkage of the gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) might use a 1.5 nm thick SiO2 gate dielectric for a gate length of less than 100 nm. Such thin gate dielectrics are a potential reliability issue and may be the most difficult issue facing the production of the upcoming generations of MOSFETs. The increasingly small and reliable integrated circuits (ICs) will likely be used in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
The semiconductor industry relies on the ability to reduce (or scale) all of the dimensions of its basic devices, such as the silicon based MOSFET, to achieve improved operational speed and power consumption. Device scaling includes scaling the gate dielectric, which has primarily been formed of silicon dioxide (SiO2). A thermally grown amorphous SiO2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have created reliability issues as the gate dielectric has become thinner. The reliability concerns suggest the use of other dielectric materials as gate dielectrics, particularly materials with higher dielectric constants.